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infineon technologies 1 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram 256 mbit synchronous dram the hyb39s256400/800/160ct(l) are four bank synchronous drams organized as 4 banks x 16mbit x4, 4 banks x 8mbit x8 and 4 banks x 4mbit x16 respectively. these synchronous devices achieve high speed data transfer rates for cas -latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with infineons advanced 0.17 m m 256mbit dram process technology. the device is designed to comply with all industry standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operates with a single 3.3v +/- 0.3v power supply and are available in tsopii packages. ? high performance: ? fully synchronous to positive clock edge ? 0 to 70 c operating temperature ? four banks controlled by ba0 & ba1 ? programmable cas latency: 2 & 3 ? programmable wrap sequence: sequential or interleave ? programmable burst length: 1, 2, 4, 8 -7.5 -8 -8a units fck 133 125 125 mhz tck3 7.5 8 8 ns tac3 5.4 6 6 ns tck2 10 10 12 ns tac2 6 6 6 ns ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read / write control (x4, x8) ? data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? power down mode ? 8192 refresh cycles / 64 ms (7,8 m s) ? random column address every clk ( 1-n rule) ? single 3.3v +/- 0.3v power supply ? lvttl interface versions ? plastic packages: p-tsopii-54 400mil width (x4, x8, x16) ? -7.5 parts for pc133 3-3-3 operation -8 parts for pc100 2-2-2 operation -8a parts for pc100 3-2-2 operation
infineon technologies 2 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram ordering information pin description and pinouts: type speed grade package description hyb 39s256400ct-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 16m x 4 sdram hyb 39s256400ct-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 16m x 4 sdram hyb 39s256400ct-8a pc100-322-620 p-tsop-54-2 (400mil) 125mhz 4b x 16m x 4 sdram hyb 39s256800ct-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 16m x 4 sdram hyb 39s256800ct-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 8m x 8 sdram hyb 39s256800ct-8a pc100-322-620 p-tsop-54-2 (400mil) 125mhz 4b x 8m x 8 sdram hyb 39s256160ct-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b x 16m x 4 sdram hyb 39s256160ct-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b x 4m x 16 sdram hyb 39s256160ct-8a pc100-322-620 p-tsop-54-2 (400mil) 125mhz 4b x 4m x 16 sdram hyb39s256xx0ctl pc100-xxx-620 p-tsop-54-2 (400mil) low power versions (on request) clk clock input dq data input /output cke clock enable dqm, ldqm, udqm data mask cs chip select vdd power (+3.3v) ras row address strobe vss ground cas column address strobe vddq power for dqs (+ 3.3v) we write enable vssq ground for dqs a0-a12 address inputs nc not connected ba0, ba1 bank select
infineon technologies 3 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram pinout for x4, x8 & x16 organised 256m-drams vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc vdd nc we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 18 19 20 21 22 23 24 25 26 27 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc udqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd 64m x 4 32m x 8 16m x 16 tsopii-54 (400 mil x 875 mil, 0.8 mm pitch)
infineon technologies 4 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram block diagram for 64m x 4 sdram ( 13 / 11 / 2 addressing) row decoder memory array bank 0 8196 x 2048 x 4 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 8196 x 2048 x 4 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 2 8196 x 2048 x 4 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 3 8196 x 2048 x 4 bi t column decoder sense amplifier & i(o) bus input buffer output buffer dq0-dq3 column address counter column address buffer row address buffer refresh counter a0 - a12, ba0, ba1 a0 - a9,a11 ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqm row addresses column addresses
infineon technologies 5 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram block diagram for 32m x 8 sdram ( 13 / 10 / 2 addressing) row decoder memory array bank 0 8192 x 1024 x 8 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 8192 x 1024 x 8 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 2 8192 x 1024 x 8 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 3 8192 x 1024 x 8 bi t column decoder sense amplifier & i(o) bus input buffer output buffer dq0-dq7 column address counter column address buffer row address buffer refresh counter a0 - a12, ba0, ba1 a0 - a9, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqm row addresses column addresses
infineon technologies 6 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram block diagram for 16m x16 sdram ( 13 / 9 / 2 addressing) row decoder memory array bank 0 8192 x 512 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 8192 x 512 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 2 8192x512 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 3 8192x512 x16 bi t column decoder sense amplifier & i(o) bus input buffer output buffer dq0-dq15 column address counter column address buffer row address buffer refresh counter a0 - a12, ba0, ba1 a0 - a8, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqmu dqml row addresses column addresses
infineon technologies 7 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas, we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a12 input level during a bank activate command cycle, a0-a12 defines the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organisation: 64m x 4 sdram can = ca9,ca11 (page length = 2048 bits) 32m x 8 sdram can = ca9 (page length = 1024 bits) 16m x 16 sdram can = ca8 (page length = 512 bits) in addition to the column address, a10(=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 (=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. ba0,ba1 input level bank select inputs. bank address inputs selects which of the four banks a command applies to. dqx input output level data input/output pins operate in the same manner as on conventional drams. dqm ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. one dqm input it present in x4 and x8 sdrams, ldqm and udqm controls the lower and upper bytes in x16 sdrams. vdd,vss supply power and ground for the input buffers and the core logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity.
infineon technologies 8 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram operation definition all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the truth table for the operation commands. note: 1. v = valid, x = dont care, l = low level, h = high level 2. cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. 3. this is the state of the banks designated by ba0, ba1 signals. 4. device state is full page burst operation, which is not supported on this device. 5. power down mode can not entry in the burst cycle. operation device state cke n-1 cke n dqm bs0 bs1 ap= a10 addr . cs ras cas we bank active idle 3 hxxvvvl lhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3 hxxvlvlhll write with autoprecharge active 3 hxxvhvlhl l read active 3 hxxvlvlhlh read with autoprecharge active 3 hxxvhvlhlh mode register set idle h x x v v v llll no operation any h x x x x x l h h h burst stop active 4 hxxxxxlhhl device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refr.) lhxxxx hxxx lhhx power down entry (precharge or active standby) idle active 5 hlxxxx hxxx lhhx power down exit any (power down) lhxxxx hxxx lhhl data write/output enableactivehxlxxxxxxx data write/output disableactivehxhxxxxxxx
infineon technologies 9 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register (mx) cas latency m6 m5 m4 latency 000reserved 001reserved 010 2 011 3 100 reserved 101 110 111 burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 100 reserved reserved 101 110 111 burst type m3 type 0 sequential 1 interleave operation mode m9 mode 0 burst read / burst write 1 burst read / single write operation mode ba0 ba1 a12
infineon technologies 10 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner.during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. the power on voltage must not exceed vdd+0.3v on any of the input pins or vdd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 m s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is divided into 4 fields. a burst length field to set the length of the burst, an addressing selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a cas latency field to set the access time at clock cycle and a operation mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. the mode set operation must be done before any activate command after the initial power up. any content of the mode register can be altered by re-executing the mode set command. all banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 133 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is 2, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. similar to the page mode of conventional drams, burst read or write accesses on any column address are possible once the ras cycle latches the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported.
infineon technologies 11 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be performed between different pages. burst length and sequence : refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self refresh mode is available. the mode restores the word lines after ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one trc delay is required prior to any access command. dqm function burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
infineon technologies 12 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the device cant remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by taking cke ?high. one clock delay is required for power down mode entry and and two clocks exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. if ca10 is high when a write command is issued, the write with auto- precharge function is initiated. the sdram automatically enters the precharge operation a time delay equal to t wr (write recovery time) after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes require a time delay twr (write recovery time) of 2 clocks minimum from the last data out to apply the precharge command.
infineon technologies 13 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram bank selection by address bits burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1xx all banks
infineon technologies 14 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram absolute maximum ratings operating temperature range .........................................................................................0 to + 70 c storage temperature range...................................................................................... C 55 to + 150 c input/output voltage .............................................................................................C 0.3 to vdd+0 .3 v power supply voltage v dd / v ddq ............................................................................ C 0.3 to + 4.6 v power dissipation............................................. ............................................................... ...........1 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operation and characteristics: t a = 0 to 70 c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v notes: 1. all voltages are referenced to vss. 2. vih may overshoot to vdd + 2.0 v for pulse width of < 4ns with 3.3v. vil may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit notes min. max. input high voltage v i h 2.0 vdd+0.3 v 1, 2 input low voltage v i l C 0.3 0.8 v 1, 2 output high voltage ( i out = C 4.0 ma) v oh 2.4 C v 3 output low voltage ( i out = 4.0 ma) v ol C0.4v3 input leakage current, any input (0 v < v i n < vddq, all other inputs = 0 v) i i (l) C 5 5 m a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C 5 5 m a parameter symbol values unit min. max. input capacitance (clk) c i 1 2.5 3.5 pf input capacitance (a0-a12, ba0,ba1,ras , cas , we , cs , cke, dqm) c i 2 2.5 3.8 pf input / output capacitance (dq) c i o 4.0 6.0 pf
infineon technologies 15 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram operating currents (t a = 0 to 70 o c, vdd = 3.3v 0.3v (recommended operating conditions unless otherwise noted) notes: 3. these parameters depend on the cycle rate. all values are measured at 133 mhz operation frequency for -7.5 devices and at 100 mhz for -8/-8a devices. input signals are changed once during tck, excepts for icc6 and for standby currents when tck=infinity. 4. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vddq current is excluded. parameter & test condition symb. -7.5 -8/-8a note max. max. operating current trc=trcmin., tck=tckmin. ouputs open, burst length = 4, cl=3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access icc1 230 170 ma 3 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) tck = min. icc2p 22ma3 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) tck = min. icc2n 40 30 ma 3 no operating current tck = min., cs = vih(min), active state ( max. 4 banks) cke>=vih(min.) icc3n 50 45 ma 3 cke<=vil(max.) icc3p 10 10 ma 3 burst operating current tck = min., read command cycling icc4 150 100 ma 3,4 auto refresh current tck = min., auto refresh command cycling icc5 240 220 ma 3 self refresh current self refresh mode, cke=0.2v standard version icc6 33ma3 l-version 1.5 1.5 ma
infineon technologies 16 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram ac characteristics 1)2) t a = 0 to 70 c; v ss = 0 v; vdd = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit -7.5 pc133- 333 -8 pc100- 222 -8a pc100- 322 min. max. min. max. min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 10 8 10 C C 8 12 C C ns ns clock frequency cas latency = 3 cas latency = 2 t ck C C 133 100 C C 125 100 C C 125 83 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac C C 5.4 6 C C 6 6 C C 6 6 ns ns 2, 3, 6 clock high pulse width t ch 2.5C3C3Cns clock low pulse width t cl 2.5C3C3Cns transition time t t 0.3 1.2 0.5 10 0.5 10 ns setup and hold times input setup time t is 1.5C2C2Cns 4 input hold time t ih 0.8C1C1Cns 4 cke setup time t cks 1.5C2C2Cns 4 cke hold time t ckh 0.8C1C1Cns 4 mode register set-up time t rsc 2C2C2Cclk power down mode entry time t sb 07.50808ns common parameters row to column delay time t rcd 20C20C20 ns 5 row precharge time t rp 20C20C20 ns 5 row active time t ras 45 100k 48 100k 48 100k ns 5 row cycle time t rc 67C70 C 70 C ns 5 activate(a) to activate(b) command period t rrd 15C16C16 ns 5
infineon technologies 17 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram cas (a) to cas (b) command period t ccd 1 C1C1Cclk refresh cycle refresh period (8192 cycles) t ref C64C64C64ms self refresh exit time t srex 1C1 1 clk read cycle data out hold time t oh 3C3C3Cns2, 6 data out to low impedance time t lz 1C0C0Cns data out to high impedance time t hz 373838ns dqm data out disable latency t dqz C2C2C2clk write cycle data input to precharge (write recovery) t wr 2C2C2Cclk dqm write mask latency t dqw 0C0C0Cclk parameter symbol limit values unit -7.5 pc133- 333 -8 pc100- 222 -8a pc100- 322 min. max. min. max. min. max.
infineon technologies 18 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram notes for ac parameters: 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is meas ured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shown in fig.1.specified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time (t t /2 - 0.5) ns has to be added to this parameter. 4. if tt is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 5. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 6. access time from clock tac is 4.6 ns for pc133 components with no termination and 0 pf load, data out hold time toh is 1.8 ns for pc133 components with no termination and 0 pf load. fig.1 50 pf i/o measurement conditions for tac and toh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
infineon technologies 19 1.00 hyb39s256400/800/160ct(l) 256mbit synchronous dram package outlines gpx09039 22.22 0.13 1) 127 54 28 0.35 +0.1 -0.05 0.1 1 0.1 10.16 0.13 0.2 11.76 0.1 0.5 does not include plastic or metal protrusion of 0.15 max per side 1) 54x 0.05 0.05 0.15 -0.03 +0.06 15? 5? 15? 5? 6 max 2.5 max 2) 3) does not include plastic protrusion of 0.25 max per side 2) does not include dambar protrusion of 0.13 max per side 3) index marking 0.8 20.8 26x 0.8 = 0.2 m 54x plastic package p-tsopii-54 (400 mil, 0.8 mm lead pitch) thin small outline package, smd
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 20 timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1 read to write interval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst write & read with auto-precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge 8. ac- parameters 9.1 ac parameters for a write timing 9.2 ac parameters for a read timing 9. mode register set 10. power on sequence and auto refresh (cbr) 11. self refresh ( entry and exit ) 12. auto refresh ( cbr ) 13. random column read ( page within same bank) 15.1 cas latency = 2 15.2 cas latency = 3 14. random column write ( page within same bank) 16.1 cas latency = 2 16.2 cas latency = 3 15. random row read ( interleaving banks) with precharge 17.1 cas latency = 2 17.2 cas latency = 3 16. random row write ( interleaving banks) with precharge 18.1 cas latency = 2 18.2 cas latency = 3 17. precharge termination of a burst
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 21 1. bank activate command cycle 2. burst read operation rc "h" or "l" t t0 (cas latency = 3) bank b row addr. activate bank b address command clk t nop nop rcd t t1 col. addr. bank b with auto precharge write b t spt03784 bank b row addr. activate bank b row addr. bank a activate bank a t nop rrd t tt spt03712 clk read a nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop nop dout a3 ck2 latency = 2 t , dq's dout a1 dout a0 dout a2 dout a2 ck3 latency = 3 t , dq's dout a0 dout a1 dout a3 (burst length = 4, cas latency = 2, 3) cas cas
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 22 3. read interrupted by a read 4. read to write intrerval 4.1 read to write interval spt03713 clk read a t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout b0 dout b1 dout b2 nop nop nop nop nop nop nop latency = 2 , dq's ck2 t ck3 latency = 3 t , dq's (burst length = 4, cas latency = 2, 3) cas cas read b dout b3 dout b1 dout a0 dout b0 dout b3 dout b2 commands = 4 + 1 = 5 cycles minimum delay between the read and write dout a0 dq's (burst length = 4, cas latency = 3) dqmx command clk nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before din b0 din b1 spt03787 din b2 dqw nop dqz t nop t t4 t5 write b nop t6 t7 nop t8 "h" or "l" write latency of dqmx
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 23 4 2. minimum read to write interval 4. 3. non-minimum read to write interval the write command must be hi-z before activate cas ck2 latency = 2 t , dq's (burst length = 4, cas latency = 2) clk dqm command nop t0 t1 bank a nop dqz t t2 t3 din a0 din a1 din a2 spt03939 din a3 1 clk interval read a write a t4 t5 nop nop t6 t7 nop t8 "h" or "l" t dqw nop cas latency = 3 ck3 cas ck2 latency = 2 t t , dq's , dq's dout a0 (burst length = 4, cas latency = 2, 3) clk dqm command nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before dout a0 dout a1 din b0 din b0 din b1 din b1 spt03940 din b2 din b2 read a dqz t nop t4 t5 write b nop t6 t7 nop t8 "h" or "l" t dqw
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 24 5. burst write operation ( extra data is ignored after termination of a burst. din a3 t4 are registered on the same clock edge. the first data element and the write nop (burst length = 4, cas latency = 2, 3) t0 command dq's clk din a1 t2 nop din a0 write a t1 din a2 nop t3 spt03790 t6 nop nop t5 nop nop t7 nop t8 don't care
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 25 6. write and read interrupt 6.1 write interrupted by a write ) 6.2 write interrupted by a read 1 clk interval spt03791 clk t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop dq's (burst length = 4, cas latency = 2, 3) nop write a din a0 din b0 din b1 din b2 din b3 write b 1 clk interval t5 nop dout b1 dout b0 input data for the write is ignored. , dq's latency = 3 ck3 cas t don't care din a0 don't care (burst length = 4, cas latency = 2, 3) clk , dq's command latency = 2 ck2 cas t nop t0 din a0 write a don't care read b t1 t2 dout b0 nop nop t4 t3 spt03719 appears on the outputs to avoid data contention. dout b2 input data must be removed from the dq's at least one clock cycle before the read data dout b1 dout b3 nop dout b3 nop dout b2 t6 t7 nop t8
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 26 7. burst write and read with auto precharge 7.1 burst write with auto-precharge ) 7.2 burst read with auto-precharge command nop nop nop write a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop bank a active nop nop din a 0 din a 1 din a 0 din a 1 * * dqs cas latency = 2 dqs cas latency = 3 begin autoprecharge bank can be reactivated after trp * t wr t wr t rp t rp nop command read a nop nop nop nop nop nop nop t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 with ap begin autoprecharge bank can be reactivated after trp * * * t rp t rp (burst length = 4, cas latency = 2,3)
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 27 8. ac parameters 8.1 ac parameters for a write timing auto precharge bank b command write with activate write with activate bank a command auto precharge bank a command command bank b addr. ap dqm dq bs hi-z rcd t ax2 ax1 ax0 ax3 rc t rax rax t as t ah rbx rbx cax activate precharge activate write command command bank a bank a command bank a bank a command spt03910 bx2 bx1 bx0 bx3 ds t t dh ay2 ay1 ay0 ay3 t wr ray ray cbx ray rp t raz raz t8 precharge begin auto bank a clk we cas ras cs cke ck2 t cs t ch cks t ch t t cl t t3 t0 t2 t1 t4 t5 t7 t6 bank b precharge begin auto t ckh t18 burst length = 4, cas latency = 2 t13 t9 t10 t12 t11 t14 t15 t17 t16 t19 t20 t22 t21 rby rby rrd t activate bank b command
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 28 8.2 ac parameters for a read timing ac2 hi-z dq activate command bank a read with bank a command auto precharge dqm addr. ap t rcd t lz t t as rax rax t ah cax rrd t command bank b read with auto precharge activate bank b command ax1 ax0 bx0 activate spt03911 command bank a bx1 t ac2 oh t hz t t ras rc t rbx rbx rbx hz t ray ray t5 t t bs we cas ras t cs cke cks t ch t t cs ch cl ck2 clk t0 t1 t2 t3 t4 precharge bank a begin auto precharge bank b begin auto t ckh burst length = 2, cas latency = 2 t6 t7 t8 t10 t9 t11 t13 t12 rp t precharge bank a command
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 29 9. mode register set set command mode register all banks precharge command any command address key t0 t1 t2 t8 rsc t t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03912 t19 t16 t15 t14 t17 t18 cas latency = 2 t20 t21 t22 bs0, bs1 a0-a9 a10, a11 cs we cas ras cke clk
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 30 10. power on sequence and auto refresh (cbr) inputs must be 200 stable for m s dqm ap dq addr. bs rp command all banks precharge hi-z ~ ~ t 1st auto refresh command ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ spt03913 mode register set command address key 8th auto refresh command ~ ~ t rc ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ command any minimum of 8 refresh cycles are required t8 we cas ras cs cke clk required ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t3 is ~ ~ ~ ~ level high t0 t2 t1 t5 t4 t7 t6 t18 2 clock min. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t13 ~ ~ ~ ~ t10 t9 t12 t11 t14 t15 t17 t16 t20 t19 t22 t21
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 31 11. self refresh (entry and exit) bs t self refresh exit command issued addr. dqm dq ap entry self refresh must be idle all banks hi-z ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ spt03919 exit command begin self refresh srex t rc self refresh command exit any t7 cs cas we ras cke clk ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t cks t0 t1 t2 ~ ~ ~ ~ t3 t4 ~ ~ ~ ~ t6 t5 t16 cks t t8 t9 t10 t11 t14 t12 t13 t15 t18 t17 t19 t20 t21 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 32 12. auto refresh (cbr) (minimum interval) addr. dqm dq ap bs auto refresh command all banks precharge command hi-z t rp t rc spt03920 command command auto refresh command bank a activate rc t rax rax ax2 bank a read ax0 ax1 ax3 cax t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 33 13. random column read (page within same bank) 13.1 cas latency = 2 ay1 addr. bs dq dqm ap activate command z hi bank a raw raw command read command bank a read bank a aw0 aw1 caw cax read bank a command aw3 aw2 ax0 ax1 ay0 cay cs we cas ras cke clk t0 ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 precharge command bank a ay2 ay3 activate command bank a raz raz spt03921 read bank a command caz burst length = 4, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 az3 az0 az1 az2
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 34 13.2 cas latency = 3 ay3 caw addr. bs dq dqm ap z hi bank a activate command read command bank a raw raw bank a command aw1 aw0 read bank a command aw2 aw3 cax read ax1 ax0 ay0 precharge command bank a ay1 ay2 cay cs we cas ras cke clk t0 ck3 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 bank a read command activate command bank a raz raz caz spt03922 burst length = 4, cas latency = 3 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 35 14. random column write (page within same bank) 14.1 cas latency = 2 dby1 addr. bs dq dqm ap activate command z hi bank a raw raw command write command bank b write bank b dbw0 dbw1 caw cax write bank b command dbw3 dbw2 dbx0 dbx1 dby0 cay cs we cas ras cke clk t0 ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 precharge command bank b dby2 dby3 activate command bank b raz raz spt03923 read bank b command caz burst length = 4, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 dbz1 dbz0 dbz2 dbz3
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 36 14.2. cas latency = 3 command write bank b cbz dbw0 addr. bs dq dqm ap bank b activate command z hi rbz rbz command bank b dbw3 dbw1 dbw2 write bank b command dbx0 dbx1 cbx write dby1 dby0 dby2 precharge command bank b dby3 cby cs we cas ras cke clk t0 ck3 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 command bank b dbz0 activate command bank b write dbz1 rbz rbz cbz spt03924 burst length = 4, cas latency = 3 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 37 15. random row read (interleaving banks) with precharge 15.1 cas latency = 2 ax2 t bs addr. dq dqm ap bank b activate command hi-z command read bank b rbx rbx rcd t cbx read activate bank a command command bank b command bx2 bx0 ac2 bx1 bank a activate bx3 bx4 rax rax command precharge bank b bx6 bx5 bx7 ax0 ax1 cax rp t rby rby cs we cas ras cke clk t0 high t ck2 t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03925 bank b command ax5 ax3 ax4 read ax6 ax7 cby by1 by0 burst length = 8, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 38 15.2 cas latency = 3 activate command bank a addr. dqm dq ap bs read bank b command command bank b activate hi-z bx1 bx0 cbx rbx rcd t rbx t ac3 activate command bank b bx6 bank a command read bx4 bx3 bx2 bx5 bank b precharge command ax0 bx7 ax2 ax1 rax cax rax rp t rby rby precharge bank a command ax7 read bank b command ax5 ax4 ax3 ax6 spt03926 by0 cby t7 we cas ras cs cke clk high ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 8, cas latency = 3 t18 t17 t19 t20 t21 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 39 16. random row write (interleaving banks) with precharge 16.1 cas latency = 2 dbx4 dax1 bs ap addr. dq dqm activate command bank a hi-z write command bank a dax0 rax rax rcd t cax command command bank b bank a command dax4 dax2 dax3 bank b activate dax5 dax6 rbx rbx command precharge bank a write dbx0 dax7 dbx1 activate dbx2 dbx3 wr cbx t rp t ray ray clk cke cs ras cas we t0 high ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 command bank a spt03927 command precharge bank b dbx7 dbx5 dbx6 write day0 day1 cay wr t day4 day3 day2 t19 burst length = 8, cas latency = 2 t16 t15 t14 t17 t18 t20 t21 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 40 16.2 cas latency = 3 dax4 addr. dqm dq ap bs command bank a bank a activate command hi-z write dax0 dax1 dax3 dax2 rax rcd t rax cax dbx4 dbx0 write command bank b bank b activate command dax6 dax5 dax7 precharge command bank a dbx2 dbx1 dbx3 cbx rbx rbx wr t rp t command bank a activate command bank a write dbx5 dbx6 day0 dbx7 precharge bank b command spt03928 day1 day2 day3 wr ray t cay ray cas ras cke clk we cs t2 high ck3 t t0 t1 t4 t3 t5 t6 t15 t7 t8 t9 t10 t11 t12 t13 t14 burst length = 8, cas latency = 3 t19 t17 t16 t18 t21 t20 t22
hyb39s256400/800/160ct(l) 256mbit synchronous dram semiconductor group 41 17. precharge termination of a burst command activate bank a t14 bs write data is masked. of a write burst. precharge termination addr. dq dqm ap command bank a activate hi z bank a write command dax0 dax1 rax rax cax command bank a command precharge bank a dax3 dax2 activate ray rp t ray ay0 command bank a read bank a precharge command ay1 ay2 cay rp t t3 cs we cas ras cke clk t0 high ck2 t t1 t2 t4 t5 t7 t6 t8 t10 t9 t11 t13 t12 precharge termination of a read burst. spt03933 bank a command precharge command bank a read az0 az1 raz caz raz az2 rp t burst length = 8 or full page, cas latency = 2 t20 t17 t15 t16 t18 t19 t21 t22

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